The present invention relates generally to hysteretic current control of inverter circuits, and more particularly to a hysteretic current control method for an inverter using variable dead time between actuation of complimentary inverter switches.
Increasingly, businesses, hospitals, utilities, and even consumers are relying on electronic and computerized equipment to conduct their daily activities. Indeed, as we progress through the new economy and the information age, the amount of reliance and the required sophistication of the electronic equipment used will only increase. Unfortunately, such increased use and sophistication of the electronic equipment brings an increased demand for reliable, quality electric power without which operations may be disrupted and critical data may be lost.
Despite the advances in the sophistication and availability of electronic and computerized equipment, the availability and reliability of high quality electric power in the quantities demanded by the growing economy has not kept pace. Indeed, while many utilities believe that rolling brown-outs provide an adequate solution to their inability to supply the electric power required by their customers, the impact that such brown-outs has on a business"" productivity and profitability is, quite simply, unacceptable.
In addition to the utilities"" inability to reliably supply the amount of electric power required, the quality of the power that is supplied often is so poor so as to affect the operation of the modem sophisticated electronic and computer equipment. Voltage sags and spikes are relatively common on the utility power lines, particularly during periods of factory shift changes in industrialized areas. Other power quality problems may be introduced by natural causes such as lightning induced voltage spikes, voltage droops caused by accidental contact with power distribution equipment by animals, tree limbs, etc. Oftentimes, these power quality perturbations have a more detrimental effect on the electronic and computerized equipment than complete power losses because the operating characteristics of the components of such equipment varies. That is, some portions of the electronic equipment may cease operating before other portions shut down, possibly resulting in erroneous operation, corrupted data, etc.
To overcome these problems, uninterruptible power supplies, line conditioners, and sophisticated power supplies have been developed. These devices and systems typically use electronic switching components to construct a regulated, high quality output voltage despite the perturbations of the input AC power from the utility. Indeed, the uninterruptible power supplies have the ability to continue to supply a high quality output voltage to the electronic and computerized equipment even during a complete loss of input AC electric power from the utility. Various well understood circuit arrangements and topologies provide this functionality.
One such well-known topology, known as a double conversion half-bridge inverter, is illustrated in simplified single line schematic form in FIG. 1. The power inputs to this inverter topology typically include the AC utility voltage 10 and, in the case of an uninterruptible power supply, a battery or other electric power storage device 12. Of course, one skilled in the art will recognize that either of these sources 10, 12 may be removed as an input without an effect on the inverter""s ability to generate an output AC voltage at its output terminals 14. In operation, a positive and a negative voltage are developed on the positive rail 16 and the negative rail 18 of the inverter respectively. The positive 20 and negative 22 bus capacitors provide the energy storage for development of the output voltage waveform during operation of the inverter. This output voltage waveform is constructed by alternately opening and closing the electronic switching elements 24, 26 as is well known in the art. Output filtering of the voltage waveform so constructed is accomplished through the output inductor 28 and filter capacitor 30.
While there are many control and command methodologies that may be used with an inverter to construct an AC output voltage waveform, most methodologies use both voltage and current control loops to ensure stable, reliable performance for the equipment coupled thereto. As with the overall methodology, various methods are well known in the art for providing both the voltage and current control and regulation. One such current control method made popular by its ease of implementation and inherent stability is a variable frequency current control topology known as hysteretic control. In simplified functional block diagrammatic form, a controller using hysteretic current control is illustrated in FIG. 2. As may be seen from this simplified block diagram, the basic inverter controller 32 receives the voltage feedback signal 34 from the inverter 36 and generates an output current command 38 to the hysteretic control block 40. The hysteretic control block also receives a current feedback signal 42 from the inverter 36. Within the hysteretic control 40, the current command signal 38 creates a current control band having a maximum current limit 38a and a minimum current control limit 38b as illustrated in FIG. 3. The actual current 42 supplied by the inverter 36 is monitored against these control limits 38a, 38b. The hysteretic control 40 then generates an output PWM signal 44 to the gate drive circuitry 46 to control the switching elements 24, 26 (see FIG. 1) of the inverter 36.
As will be recognized by those skilled in the art, the hysteretic current control provides a method of controlling the output current of the inverter where the instantaneous output current is allowed to vary within the current control band xcex94I defined by the maximum current limit 38a, and the minimum current limit 38b. This hysteretic control 40 operates to turn on the upper switching element 24 (see FIG. 1) when the current 42 is below the maximum current limit 38a. As the current 42 rises to this maximum limit 38a, the hysteretic control 40 operates to turn off the switching element 24 and to turn on the switching element 26. This causes the instantaneous current 42 to fall. Once the current 42 reaches the minimum current limit 38b, the hysteretic control 40 operates to turn off the lower switching element 26 and to turn on the upper switching element 24 to again cause the instantaneous current 42 to rise. This alternative switching of the switching elements 24, 26 continues to maintain the instantaneous current 42 within the upper and lower current control limits 38a, 38b in a known manner.
The time T1 between these events defines the switching frequency of the hysteretic control. This time T1 will typically vary as the output voltage rises and falls over the AC cycle. Near the peak of the AC output voltage cycle, the actual inverter current 42 will rise rapidly and fall very slowly, and therefore the frequency of switching will be greatly decreased. Near the zero cross of the AC outlet voltage waveform, the current will rise and fall relatively rapidly, therefore increasing the switching frequency commanded by the hysteretic control. A typical variation in the output switching frequency resulting from the hysteretic control 40 may be in the range of 10:1 in frequency when going from the zero cross to peak AC. Unfortunately, at the higher switching rates, the pure hysteretic control results in excessive heating of the inverter switches due to the inherent switching losses that occur each time the switching devices are transitioned. At the lower switching rates, excessive harmonic distortion may occur if the rate drops too low.
There exists, therefore, a need in the art to provide a control mechanism that allows the use of hysteretic current control, but that better controls the switching frequency variation over the AC voltage waveform to prevent excessive heating of the inverter switching elements.
In view of the above, it is an object of the present invention to provide a new and improved inverter control methodology. More particularly, it is an object of the present invention to provide a new and improved inverter control that uses hysteretic current control, but which allows for control of the switching frequency to reduce undesirable effects which may result from typical hysteretic control. It is a further object of the present invention to provide a new and improved uninterruptible power supply that uses such control.
In one embodiment, a current control method for use with an inverter having at least two switching elements that are controllable to construct an AC output waveform in accordance with a pulse-width modulated (PWM) control signal from a hysteretic control circuit is presented. This method comprises the steps of monitoring the duration of each PWM event, classifying these events into at least two classifications, comparing each of the PWM event""s classifications to the previous event classification, and selecting a dead time delay based on this comparison. The method commands off one of the switching elements and delays for the selected dead time delay the commanding on of the other of the switching elements.
Preferably, the step of classifying comprises the step of classifying each of the PWM events as one of long duration and short duration. Further, the step of selecting a dead time delay preferably comprises the steps of selecting a minimum dead time delay, and adding a frequency control dead time delay component when the step of comparing identifies two consecutive short events. In an embodiment wherein the first switching element couples a positive rail to an output of the inverter and the second switching element couples a negative rail to the output of the inverter, the step of commanding off one of the switching elements preferably comprises the step of commanding off the first switching element. Further, the step of delaying for the selected dead time delay the commanding on of another of the switching elements comprises delaying the commanding on of the second switching element.
In a further embodiment, the step of commanding off one of the switching elements comprises commanding off the second switching element, and the step of delaying a commanding on of another of the switching elements comprises delaying the commanding on of the first switching element. Preferably, transitions from the first switching element to the second switching element are delayed for the minimum dead time delay, and transitions from the second switching element to the first switching element are delayed for the selected dead time delay.
In a further embodiment, the step of selecting a dead time delay comprises the steps of selecting a first dead time when two consecutive events of a first classification are detected, selecting a second dead time when two consecutive events of a second classification are detected, and maintaining a previous selected dead time when two consecutive events are of different classifications. An embodiment of the method further comprises the step of selecting a third dead time during an overcurrent condition.
In an alternate embodiment, a method of controlling a switching frequency of inverter switches for use with an inverter having at least a first and a second switching element controllable to construct an AC output waveform in accordance with a pulse-width modulated (PWM) control signal from a hysteretic control circuit is presented. This method comprises the steps of monitoring a duration of each PMW event, injecting a first dead time delay between transitions of the switching elements when the duration is greater than a preset time, and injecting a second dead time delay between transitions of the switching elements when the duration is less than the preset time. Preferably, the method further comprises the steps of comparing the duration of a current PWM event to the duration of an immediately preceding PWM event, maintaining the injection of the first dead time delay once selected until the duration of two consecutive PWM events is less than the preset time, and maintaining the injection of the second dead time delay once selected until the duration of two consecutive PWM events is greater than the preset time.
In a further embodiment, the step of injecting the first dead time delay comprises the step of injecting a minimum dead time delay of duration minimally sufficient to prevent a current shoot through condition. Further, the step of injecting the second dead time delay comprises the step of injecting the minimum dead time delay plus a frequency control component of duration to cumulatively reduce excessive heating of the switching elements. Alternatively, the method further comprises the steps of detecting an overcurrent condition and injecting a third dead time delay between transitions of the switching elements in response.
Also presented is a controller for use with an inverter having at least a first and a second switching element controllable to construct an output AC waveform for use by equipment. The controller preferably comprises an inverter control circuit using hysteretic current control. The control circuit generates a pulse-width modulated (PWM) inverter control signal to control transitions of the switching elements to construct the output AC waveform in response to a voltage and a current feedback from the inverter output. The PWM inverter control signal has PWM events defined by transitions of the signal. The controller further comprises a logic driver circuit coupled to receive the PWM inverter control signal. This logic circuit preferably generates a first and a second drive signal to transition the first and second switching elements in response to the PWM inverter control signal. The logic driver circuit monitors the duration of the PWM events and delays the generation of the first and the second drive signals for one of at least a first and a second dead time based on the duration of the PWM events.
The logic driver circuit generates a first dead time of duration minimally sufficient to prevent a shoot through condition from occurring, and a second dead time comprising the first dead time plus an additional frequency control delay of duration to cumulatively reduce a switching frequency governed by the PWM inverter control signal. The hysteretic current control generates the PWM inverter control signal to maintain the current feedback within a maximum and a minimum current limit. However, the logic driver circuit uses the second dead time to delay generation of the first and the second drive signals in a manner to allow the current feedback to fall below the minimum current limit to reduce a switching frequency of the switching elements. Alternatively, the hysteretic current control generates the PWM inverter control signal to maintain the current feedback within a current control band, and the logic driver circuit uses the second dead time to delay generation of the first and the second drive signals in a manner to allow the current feedback to exceed the current control band to reduce a switching frequency of the switching elements.
In a further embodiment, the logic driver circuit classifies the duration of the PWM events into at least a first and a second class, and delays the generation of the first and the second drive signals for the first dead time when the PWM events are of the first class, and for the second dead time when the PWM events are of the second class. Preferably, the logic driver circuit maintains a current selected dead time until at least two consecutive PWM events are classified as other than that required for the current selected dead time.
Also presented is an uninterruptible power supply (UPS) comprising an inverter having a first input adapted to receive line AC power, a second input adapted to receive stored DC power, and an inverter output. The inverter has at least a first and a second switching element controllable to supply an AC voltage and current output from the line AC power and the stored DC power. The UPS also comprises a controller having a voltage and a current feedback input coupled to the inverter output, and a first and a second drive signal output operatively coupled to the first and the second switching elements to control construction of the AC voltage and current output. The controller uses hysteretic current control to generated a pulse-width modulated (PWM) control signal, and includes a logic driver circuit operative to generated the first and the second drive signals in response to the PWM control signal. Preferably, the logic driver circuit monitors the duration of each pulse-width of the PWM control signal and inserts a dead time delay between transitions of the first and the second drive signal. This dead time delay has a duration based on the duration of each pulse-width of the PWM control signal.
In a further embodiment, the logic driver circuit generates a first dead time of duration minimally sufficient to prevent a shoot through condition from occurring, and a second dead time comprising the first dead time plus an additional frequency control delay of duration to cumulatively reduce a switching frequency governed by the PWM control signal. The logic driver circuit uses the first dead time when the duration of a pulse-width is greater than a predetermined threshold, and uses the second dead time when the duration of a pulse-width is less than the predetermined threshold. Preferably, the logic driver circuit maintains a currently selected dead time delay until at least two consecutive pulse-widths have a duration that dictate a different dead time delay. Additionally, in one embodiment the logic driver inserts a third dead time delay when the controller detects an overcurrent condition.
Other objectives and advantages of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.